Techniques for forming diffusion regions of semiconductor devices include ion implantation, gaseous phase diffusion, and solid phase diffusion. With ion implantation, disadvantageously, the depth of resulting diffusion regions is shallow, namely, only on the order of 1 .mu.m, and a high temperature of from 700.degree. to 800.degree. C. is required for annealing. Sufficient depth can be achieved when gaseous phase diffusion is employed, but, disadvantageously, the area of a resulting diffusion region is small and a high temperature of 700.degree.-800.degree. C. for annealing is required. In contrast, solid phase diffusion can provide a large depth and a large area diffusion region, and the annealing temperature is lower, namely, 400.degree.-500.degree. C. Thus, solid phase diffusion is suitable for forming diffusion regions of semiconductor devices.
An example of a conventional technique of forming a diffusion region by means of solid phase diffusion is now described with reference to FIGS. 1(a)-l(h), which illustrate fabrication of an InGaAs/InP photodiode.
As shown in FIG. 1(a), on an n.sup.+ -type InP substrate 1, an n.sup.- -type InGaAs light absorbing layer 2, an n.sup.- -type InP window layer 3, and n.sup.- -type InGaAs contact layer 4, which are epitaxial layers, are uniformly grown in the named order by, for example, gaseous phase growth. In this case, the lattice constant difference between the n.sup.- -type InGaAs light absorbing layer 2 and n+-type InGaAs contact layer 4 is within a range of .+-.0.3 %.
In the step shown in FIG. 1(b), a SiN masking film 7 is deposited uniformly over the n.sup.- -type InGaAs contact layer 4 by means of, for example, plasma CVD. Then, photolithography is employed to form an aperture A, using an etchant, such as hydrofluoric acid, only in that portion of the film 7 through which solid phase diffusion is to be carried out.
Then, as shown in FIG. 1(c), a uniform ZnO diffusion source layer 8 and a uniform SiO.sub.2 capping layer 9 each having a thickness of about 1000 .ANG. are successively desposited by sputtering on the masking film 7 and the layer 4 exposed through the aperture A.
In the step shown in FIG. 1(d), the structure shown in FIG. 1(c) is subjected to heat treatment in an N.sub.2 gas atmosphere at a temperature of about 500.degree. C. for several tens of minutes to effect diffusion of Zn, which results in a p-type region 10. (In FIG. 1(d), a broken line indicates a diffusion front.)
Next, the SiO.sub.2 layer 9, the ZnO diffusion source layer 8, and the SiN layer 7 are removed by selective etching, using an etchant, such as hydrofluoric acid, which results in a structure shown in FIG. 1(e). Then, using nitric acid for selective etching, the n.sup.- -type InGaAs contact layer 4 is removed, leaving a p-type inversion layer 4a which is part of that portion of the layer 4 which has been inverted to p-type. This results in a structure shown on 1(f). The top surface of the structure shown in FIG. 1(f) is covered with an SiN film 11, leaving the top surface of the p-type inversion layer 4a uncovered, as shown in FIG. 1(g).
Finally, an Au/Ti electrode 12 is formed for connection to the p-type inversion layer 4a, and an Au/AuGe electrode 13 is formed on the opposite surface of the substrate 1, as shown in FIG. 1(h).
According to the conventional solid phase diffusion, a solid phase diffusion source is vapor deposited directly on an epitaxial layer of a resulting semiconductor device. Accordingly, when the structure is subjected to heat treatment, distortions are produced due to differences in physical constants, such as thermal expansion coefficients, of the two materials, which could result in defects, such as dislocation, in epitaxial layers forming the device. Such defects could cause an increase in leakage current.